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FPL
2010
Springer
170views Hardware» more  FPL 2010»
14 years 11 months ago
IP Based Configurable SIMD Massively Parallel SoC
Significant advances in the field of configurable computing have enabled parallel processing within a single FieldProgrammable Gate Array (FPGA) chip. This paper presents the imple...
Mouna Baklouti, Mohamed Abid, Philippe Marquet, Je...
FCCM
2006
IEEE
144views VLSI» more  FCCM 2006»
15 years 7 months ago
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
Robert G. Dimond, Oskar Mencer, Wayne Luk
DATE
2005
IEEE
109views Hardware» more  DATE 2005»
15 years 7 months ago
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...
ICNP
1998
IEEE
15 years 6 months ago
Distributed Packet Rewriting and its Application to Scalable Server Architectures
To construct high performance Web servers, system builders are increasingly turning to distributed designs. An important challenge that arises in such designs is the need to direc...
Azer Bestavros, Mark Crovella, Jun Liu, David Mart...
IWSOC
2005
IEEE
112views Hardware» more  IWSOC 2005»
15 years 7 months ago
Practical Techniques for Performance Estimation of Processors
Performance estimation of processor is important to select the right processor for an application. Poorly chosen processors can either under perform very badly or over perform but...
Abhijit Ray, Thambipillai Srikanthan, Wu Jigang