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» The Price of Routing in FPGAs
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FCCM
2006
IEEE
108views VLSI» more  FCCM 2006»
15 years 5 months ago
A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism
This paper presents a novel reconfigurable data flow processing architecture that promises high performance by explicitly targeting both fine- and course-grained parallelism. This...
Charles L. Cathey, Jason D. Bakos, Duncan A. Buell
FPL
2003
Springer
128views Hardware» more  FPL 2003»
15 years 4 months ago
Case Study of a Functional Genomics Application
Although microarrays are already having a tremendous impact on biomedical science, they still present great computational challenges. We examine a particular problem involving the...
Tom Van Court, Martin C. Herbordt, Richard J. Bart...
FPGA
2001
ACM
128views FPGA» more  FPGA 2001»
15 years 3 months ago
Using sparse crossbars within LUT
In FPGAs, the internal connections in a cluster of lookup tables (LUTs) are often fully-connected like a full crossbar. Such a high degree of connectivity makes routing easier, bu...
Guy G. Lemieux, David M. Lewis
FPL
1999
Springer
74views Hardware» more  FPL 1999»
15 years 3 months ago
On Tool Integration in High-Performance FPGA Design Flows
Abstract. High-performance design flows for FPGAs often rely on module generators to counter coarse logic-block granularity and limited routing resources, However, the very flexi...
Andreas Koch
FPL
1997
Springer
130views Hardware» more  FPL 1997»
15 years 3 months ago
Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research
: The paper first proposes requirements for an ideal platform for codesign research. A new board developed at Imperial College, the Riley-2, is shown to meet these requirements. It...
Patrick I. Mackinlay, Peter Y. K. Cheung, Wayne Lu...