5640 search results - page 174 / 1128 » The Primacy of Process Architecture |
107
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ISCAS
2003
IEEE
15 years 6 months ago
2003
IEEE
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
PARELEC
2000
IEEE
15 years 5 months ago
2000
IEEE
The purpose of this paper is to demonstrate the implementation of an adaptable parallel architecture capable of system to task adaptation. The system implementation was based on X...
101
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VLSID
2000
IEEE
15 years 5 months ago
2000
IEEE
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
148
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ASAP
1996
IEEE
15 years 4 months ago
1996
IEEE
A datapath synthesis system (DPSS) for a bus-based wavefront array architecture, called rDPA (reconfigurable datapath architecture), is presented. An internal data bus to the arra...
KONVENS
1992
15 years 4 months ago
1992
: We consider communication between modules in an integrated architecture for Speech and Natural Language (NL), in particular the communication with the semantics module. In an int...