Sciweavers

6271 search results - page 1154 / 1255
» The RACE network architecture
Sort
View
ASPDAC
2000
ACM
104views Hardware» more  ASPDAC 2000»
15 years 5 months ago
Design of digital neural cell scheduler for intelligent IB-ATM switch
— We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-bas...
J.-K. Lee, Seung-Min Lee, Mike Myung-Ok Lee, D.-W....
89
Voted
SC
2000
ACM
15 years 5 months ago
Automatically Tuned Collective Communications
The performance of the MPI’s collective communications is critical in most MPI-based applications. A general algorithm for a given collective communication operation may not giv...
Sathish S. Vadhiyar, Graham E. Fagg, Jack Dongarra
90
Voted
SIGOPSE
2000
ACM
15 years 5 months ago
The data management problem in post-pc devices and a solution
The demand for network-enabled limited-footprint mobile devices is increasing rapidly. A central challenge that must be addressed in order to use these next-generation devices eff...
Ramakrishna Gummadi, Randy H. Katz
165
Voted
PLDI
1999
ACM
15 years 5 months ago
Enhanced Code Compression for Embedded RISC Processors
This paper explores compiler techniques for reducing the memory needed to load and run program executables. In embedded systems, where economic incentives to reduce both ram and r...
Keith D. Cooper, Nathaniel McIntosh
HPDC
1999
IEEE
15 years 5 months ago
Resource Co-Allocation in Computational Grids
Applications designed to execute on "computational grids" frequently require the simultaneous co-allocation of multiple resources in order to meet performance requiremen...
Karl Czajkowski, Ian T. Foster, Carl Kesselman
« Prev « First page 1154 / 1255 Last » Next »