6271 search results - page 159 / 1255 » The RACE network architecture |
96
Voted
IPPS
1998
IEEE
15 years 5 months ago
1998
IEEE
This work deals with the scheduling problem of a directed acyclic graph with interprocessor communication delays. The objective is to minimize the makespan, taking into account the...
111
Voted
DSS
2007
15 years 23 days ago
2007
This paper describes a service-based P2P overlay network architecture to support a collaborative environment for solving complex business processes over the network. In the propos...
107
Voted
HPCA
2006
IEEE
16 years 1 months ago
2006
IEEE
An important means of validating the design of commercial-grade shared memory multiprocessors is to run a large number of pseudo-random test programs on them. However, when intent...
102
Voted
HPCA
2005
IEEE
16 years 1 months ago
2005
IEEE
Improvements in semiconductor technology now enable Chip Multiprocessors (CMPs). As many future computer systems will use one or more CMPs and support shared memory, such systems ...
88
Voted
IEEEPACT
2009
IEEE
15 years 7 months ago
2009
IEEE
Abstract—As programmers are asked to manage more complicated parallel machines, it is likely that they will become increasingly dependent on tools such as multi-threaded data rac...