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131
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TCAD
2010
110views more  TCAD 2010»
14 years 10 months ago
Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power
Abstract--In sub-100 nm CMOS processes, delay and leakage power reduction continue to be among the most critical design concerns. We propose to exploit the recent availability of f...
Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Ha...
TCAD
2010
168views more  TCAD 2010»
14 years 10 months ago
An MILP-Based Performance Analysis Technique for Non-Preemptive Multitasking MPSoC
For real-time applications, it is necessary to estimate the worst-case performance early in the design process without actual hardware implementation. While the non-preemptive task...
Hoeseok Yang, Sungchan Kim, Soonhoi Ha
127
Voted
TCAD
2010
90views more  TCAD 2010»
14 years 10 months ago
Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration
The last decade has witnessed the emergence of the application-specific instruction-set processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user ...
Ajay K. Verma, Philip Brisk, Paolo Ienne
138
Voted
TCAD
2010
118views more  TCAD 2010»
14 years 10 months ago
Design Tools for Digital Microfluidic Biochips: Toward Functional Diversification and More Than Moore
Abstract--Microfluidics-based biochips enable the precise control of nanoliter volumes of biochemical samples and reagents. They combine electronics with biology, and they integrat...
Krishnendu Chakrabarty, Richard B. Fair, Jun Zeng
TCAD
2010
121views more  TCAD 2010»
14 years 10 months ago
Translation Validation of High-Level Synthesis
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
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