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» The Semantics of Future and Its Use in Program Optimizations
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CAV
2009
Springer
215views Hardware» more  CAV 2009»
16 years 6 months ago
Homer: A Higher-Order Observational Equivalence Model checkER
We present HOMER, an observational-equivalence model checker for the 3rd-order fragment of Idealized Algol (IA) augmented with iteration. It works by first translating terms of the...
David Hopkins, C.-H. Luke Ong
CODES
2007
IEEE
16 years 12 days ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
ASPLOS
2011
ACM
14 years 9 months ago
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such a...
Luke Dalessandro, François Carouge, Sean Wh...
SPE
2008
89views more  SPE 2008»
15 years 6 months ago
The Runabout
This paper presents a variation of the visitor pattern which allows programmers to write visitor-like code in a concise way. The Runabout is a library extension that adds a limited...
Christian Grothoff
SIGADA
2004
Springer
15 years 11 months ago
Information systems security engineering: a critical component of the systems engineering lifecycle
The purpose of this research paper is to illustrate the industrial and federal need for Information Systems Security Engineering (ISSE) in order to build Information Assurance (IA...
James F. Davis