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» The Simulation and Design of Integrated Inductors
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DAC
2008
ACM
15 years 11 months ago
Enhancing timing-driven FPGA placement for pipelined netlists
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
Kenneth Eguro, Scott Hauck
DAC
2006
ACM
15 years 3 months ago
SystemC transaction level models and RTL verification
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
Stuart Swan
AUTOMATICA
2006
98views more  AUTOMATICA 2006»
14 years 10 months ago
Stabilization of sampled-data nonlinear systems via backstepping on their Euler approximate model
Two integrator backstepping designs are presented for digitally controlled continuous-time plants in special form. The controller designs are based on the Euler approximate discre...
Dragan Nesic, Andrew R. Teel
TVLSI
2010
14 years 4 months ago
Variation-Aware System-Level Power Analysis
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
GLVLSI
2003
IEEE
180views VLSI» more  GLVLSI 2003»
15 years 3 months ago
3D direct vertical interconnect microprocessors test vehicle
The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated C...
John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan...