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» The Simulation and Design of Integrated Inductors
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ICCAD
2004
IEEE
128views Hardware» more  ICCAD 2004»
15 years 7 months ago
Power estimation for cycle-accurate functional descriptions of hardware
— Cycle-accurate functional descriptions (CAFDs) are being widely adopted in integrated circuit (IC) design flows. Power estimation can potentially benefit from the inherent in...
Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj...
CASES
2004
ACM
15 years 3 months ago
High-level power analysis for on-chip networks
As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power in...
Noel Eisley, Li-Shiuan Peh
DAC
2006
ACM
15 years 11 months ago
Process variation aware OPC with variational lithography modeling
Optical proximity correction (OPC) is one of the most widely used resolution enhancement techniques (RET) in nanometer designs to improve subwavelength printability. Conventional ...
Peng Yu, Sean X. Shi, David Z. Pan
79
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ICCCN
2008
IEEE
15 years 4 months ago
Policy Distribution Methods for Function Parallel Firewalls
—Parallel firewalls offer a scalable low latency design for inspecting packets at high speeds. Typically consisting of an array of m firewalls, these systems filter arriving p...
Michael R. Horvath, Errin W. Fulp, Patrick Wheeler
GLVLSI
2003
IEEE
173views VLSI» more  GLVLSI 2003»
15 years 3 months ago
40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications
An embedded 40 MHz FIFO buffer for use in mixed-signal information processing applications is presented. The buffer design uses a 1T DRAM topology for its unit memory cell compone...
Michael I. Fuller, James P. Mabry, John A. Hossack...