Sciweavers

1728 search results - page 317 / 346
» The Size of Power Automata
Sort
View
ICRA
2006
IEEE
225views Robotics» more  ICRA 2006»
15 years 5 months ago
Constraint Optimization Coordination Architecture for Search and Rescue Robotics
— The dangerous and time sensitive nature of a disaster area makes it an ideal application for robotic exploration. Our long term goal is to enable humans, software agents, and a...
Mary Koes, Illah R. Nourbakhsh, Katia P. Sycara
IEEEPACT
2006
IEEE
15 years 5 months ago
Self-checking instructions: reducing instruction redundancy for concurrent error detection
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
15 years 5 months ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang
ISCAS
2006
IEEE
133views Hardware» more  ISCAS 2006»
15 years 5 months ago
Neuronal ion-channel dynamics in silicon
Abstract— We present a simple silicon circuit for modelling voltagedependent ion channels found within neural cells, capturing both the gating particle’s sigmoidal activation (...
Kai M. Hynna, Kwabena Boahen
MICRO
2006
IEEE
82views Hardware» more  MICRO 2006»
15 years 5 months ago
Yield-Aware Cache Architectures
One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields ha...
Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonath...