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» The Size of Power Automata
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PACS
2000
Springer
132views Hardware» more  PACS 2000»
15 years 3 months ago
An Adaptive Issue Queue for Reduced Power at High Performance
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue ...
Alper Buyuktosunoglu, Stanley Schuster, David Broo...
FCCM
2008
IEEE
112views VLSI» more  FCCM 2008»
15 years 6 months ago
Power-Aware and Branch-Aware Word-Length Optimization
Power reduction is becoming more important as circuit size increases. This paper presents a tool called PowerCutter which employs accuracy-guaranteed word-length optimization to r...
William G. Osborne, José Gabriel F. Coutinh...
DAC
1997
ACM
15 years 4 months ago
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
Howard H. Chen, David D. Ling
ISLPED
2007
ACM
138views Hardware» more  ISLPED 2007»
15 years 1 months ago
Power optimal MTCMOS repeater insertion for global buses
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
Hanif Fatemi, Behnam Amelifard, Massoud Pedram
ISLPED
1997
ACM
114views Hardware» more  ISLPED 1997»
15 years 4 months ago
Analysis of power consumption in memory hierarchies
In this paper, we note and analyze a key trade-off: as the complexity of caches increases (higher set-associativity, larger block size, and larger overall size), the power consume...
Patrick Hicks, Matthew Walnock, Robert Michael Owe...