1728 search results - page 72 / 346 » The Size of Power Automata |
WINET
2008
14 years 11 months ago
2008
Abstract There exist accurate calculation methods for estimation of interference power sum statistics in fixedtopology wireless networks based on the log-normal shadowing radio mod...
ISCAS
2006
IEEE
15 years 6 months ago
2006
IEEE
The optimum tapered structure for RLC inter- RLCinterconnect connect to minimize transient power dissipation is determined. Wire tapering can reduce the power dissipated by a circu...
112
click to vote
PATMOS
2010
Springer
14 years 9 months ago
2010
Springer
In most modern processor designs the L1 data cache has become a major consumer of power due to its increasing size and high frequency access rate. In order to reduce this power con...
107
click to vote
ASAP
2009
IEEE
14 years 9 months ago
2009
IEEE
This paper examines the architecture, algorithm and implementation of a switch-based multi-processor realization of the fast Fourier transform (FFT). The architecture employs M pr...
IWSOC
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper explores the design and optimization of Quasi-Floating Gate MOS techniques to lowvoltage/low-power digital circuitry. The simulated power consumption of standard CMOS g...