1728 search results - page 73 / 346 » The Size of Power Automata |
ISSS
2002
IEEE
15 years 4 months ago
2002
IEEE
We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for i...
DATE
1999
IEEE
15 years 4 months ago
1999
IEEE
This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally...
CAMP
2005
IEEE
15 years 5 months ago
2005
IEEE
— In this paper, a programmable analog retina is presented and compared with state of the art MPU for embedded imaging applications. The comparison is based on the energy require...
PCRCW
1997
Springer
15 years 4 months ago
1997
Springer
High performance portable and space-borne systems continue to demand increasing computation speeds while concurrently attempting to satisfy size, weight, and power constraints. As...
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DAC
2008
ACM
15 years 1 months ago
2008
ACM
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...