1728 search results - page 79 / 346 » The Size of Power Automata |
ISLPED
2005
ACM
15 years 5 months ago
2005
ACM
Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan lat...
FPL
2009
Springer
15 years 4 months ago
2009
Springer
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
ISLPED
1997
ACM
15 years 4 months ago
1997
ACM
In this paper1 we propose a novel approach to synthesis for low power under tight timing constraints. Starting from a mapped netlist, we apply a powerful generalized matching algo...
111
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DAC
2004
ACM
15 years 3 months ago
2004
ACM
This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests ...
114
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NOMS
2008
IEEE
15 years 6 months ago
2008
IEEE
— With the continued growth of computing power and reduction in physical size of enterprise servers, the need for actively managing electrical power usage in large datacenters is...