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» The Size of Power Automata
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ISCAS
2005
IEEE
138views Hardware» more  ISCAS 2005»
15 years 5 months ago
Transition time bounded low-power clock tree construction
— Recently power becomes a significant issue in clock network design for high-performance ICs because the clock network consumes a large portion of the total power in the whole s...
Min Pan, Chris C. N. Chu, J. Morris Chang
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
14 years 11 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
VLSID
2004
IEEE
146views VLSI» more  VLSID 2004»
16 years 8 days ago
CMOS Circuit Design for Minimum Dynamic Power and Highest Speed
{A new low-power design method produces CMOS circuits that consume the least dynamic power at the highest speed permitted under the technology constraint. A gate is characterized b...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
ICPP
2003
IEEE
15 years 5 months ago
Quorum-Based Asynchronous Power-Saving Protocols for IEEE 802.11 Ad Hoc Networks
This paper investigates the power mode management problem for an IEEE 802.11-based mobile ad hoc network (MANET) that allows mobile hosts to tune to the power-saving (PS) mode. The...
Jehn-Ruey Jiang, Yu-Chee Tseng, Chih-Shun Hsu, Ten...
SIGMETRICS
2010
ACM
187views Hardware» more  SIGMETRICS 2010»
15 years 4 months ago
Can multipath mitigate power law delays?: effects of parallelism on tail performance
—Parallelism has often been used to improve the reliability and efficiency of a variety of different engineering systems. In this paper, we quantify the efficiency of paralleli...
Jian Tan, Wei Wei, Bo Jiang, Ness Shroff, Donald F...