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HPCA
2011
IEEE
14 years 1 months ago
ACCESS: Smart scheduling for asymmetric cache CMPs
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primari...
Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishanka...
ISCA
2011
IEEE
287views Hardware» more  ISCA 2011»
14 years 1 months ago
Scalable power control for many-core architectures running multi-threaded applications
Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cann...
Kai Ma, Xue Li, Ming Chen, Xiaorui Wang
PLDI
2011
ACM
14 years 17 days ago
A case for an SC-preserving compiler
The most intuitive memory consistency model for shared-memory multi-threaded programming is sequential consistency (SC). However, current concurrent programming languages support ...
Daniel Marino, Abhayendra Singh, Todd D. Millstein...
CCS
2011
ACM
13 years 9 months ago
Eliminating the hypervisor attack surface for a more secure cloud
Cloud computing is quickly becoming the platform of choice for many web services. Virtualization is the key underlying technology enabling cloud providers to host services for a l...
Jakub Szefer, Eric Keller, Ruby B. Lee, Jennifer R...
CF
2011
ACM
13 years 9 months ago
SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors
Dynamic Information Flow Tracking (DIFT) is a powerful technique that can protect unmodified binaries from a broad range of vulnerabilities such as buffer overflow and code inj...
Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazal...