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ISCA
1995
IEEE
98views Hardware» more  ISCA 1995»
15 years 1 months ago
Instruction Fetching: Coping with Code Bloat
Previous research has shown that the SPEC benchmarks achieve low miss ratios in relatively small instruction caches. This paper presents evidence that current software-development...
Richard Uhlig, David Nagle, Trevor N. Mudge, Stuar...
LCPC
2005
Springer
15 years 3 months ago
Compiler Control Power Saving Scheme for Multi Core Processors
With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten developmen...
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroak...
PLDI
2010
ACM
15 years 2 months ago
Software data spreading: leveraging distributed caches to improve single thread performance
Single thread performance remains an important consideration even for multicore, multiprocessor systems. As a result, techniques for improving single thread performance using mult...
Md Kamruzzaman, Steven Swanson, Dean M. Tullsen
ICIP
2000
IEEE
15 years 2 months ago
Switched Error Concealment and Robust Coding Decisions in Scalable Video Coding
This work introduces two complementary techniques to improve the packet loss resilience of scalable video coding systems. First, a “switch per-pixel” error concealment (SPEC) ...
Rui Zhang, Shankar L. Regunathan, Kenneth Rose
ICCD
2004
IEEE
74views Hardware» more  ICCD 2004»
15 years 6 months ago
Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2
In this paper we present a clustered, multiple-clock domain (CMCD) microarchitecture that combines the benefits of both clustering and Globally Asynchronous Locally Synchronous (G...
Grigorios Magklis, José González, An...