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MICRO
2007
IEEE
120views Hardware» more  MICRO 2007»
15 years 4 months ago
Scavenger: A New Last Level Cache Architecture with Global Block Priority
Addresses suffering from cache misses typically exhibit repetitive patterns due to the temporal locality inherent in the access stream. However, we observe that the number of inte...
Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Maina...
WMPI
2004
ACM
15 years 3 months ago
A case for multi-level main memory
Current trends suggest that the number of memory chips per processor chip will increase at least a factor of ten in seven years. This will make DRAM cost, the space and the power i...
Magnus Ekman, Per Stenström
ICS
2004
Tsinghua U.
15 years 3 months ago
Effective stream-based and execution-based data prefetching
With processor speeds continuing to outpace the memory subsystem, cache missing memory operations continue to become increasingly important to application performance. In response...
Sorin Iacobovici, Lawrence Spracklen, Sudarshan Ka...
MICRO
2003
IEEE
124views Hardware» more  MICRO 2003»
15 years 3 months ago
Optimum Power/Performance Pipeline Depth
The impact of pipeline length on both the power and performance of a microprocessor is explored both theoretically and by simulation. A theory is presented for a wide range of pow...
Allan Hartstein, Thomas R. Puzak
ISLPED
2003
ACM
88views Hardware» more  ISLPED 2003»
15 years 3 months ago
Reducing data cache energy consumption via cached load/store queue
High-performance processors use a large set–associative L1 data cache with multiple ports. As clock speeds and size increase such a cache consumes a significant percentage of t...
Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru...