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DATE
2006
IEEE
82views Hardware» more  DATE 2006»
15 years 5 months ago
Value-based bit ordering for energy optimization of on-chip global signal buses
In this paper, we present a technique that exploits the statistical behavior of data values transmitted on global signal buses to determine an energy-efficient ordering of bits t...
Krishnan Sundaresan, Nihar R. Mahapatra
DATE
2006
IEEE
89views Hardware» more  DATE 2006»
15 years 5 months ago
Automatic insertion of low power annotations in RTL for pipelined microprocessors
We propose instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level (RTL) in order to achieve lower power dissipation....
Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt ...
ASPDAC
2006
ACM
103views Hardware» more  ASPDAC 2006»
15 years 5 months ago
Prefetching-aware cache line turnoff for saving leakage energy
Abstract— While numerous prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention. This paper studies this i...
Ismail Kadayif, Mahmut T. Kandemir, Feihui Li
ISCA
2005
IEEE
87views Hardware» more  ISCA 2005»
15 years 5 months ago
A Robust Main-Memory Compression Scheme
Lossless data compression techniques can potentially free up more than 50% of the memory resources. However, previously proposed schemes suffer from high access costs. The propose...
Magnus Ekman, Per Stenström
ISCA
2005
IEEE
115views Hardware» more  ISCA 2005»
15 years 5 months ago
The V-Way Cache: Demand Based Associativity via Global Replacement
As processor speeds increase and memory latency becomes more critical, intelligent design and management of secondary caches becomes increasingly important. The efficiency of curr...
Moinuddin K. Qureshi, David Thompson, Yale N. Patt