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IEEEPACT
2000
IEEE
15 years 4 months ago
Region Formation Analysis with Demand-Driven Inlining for Region-Based Optimization
Region-based compilation repartitions a program into more desirable compilation units for optimization and scheduling, particularly beneficial for ILP architectures. With region-...
Tom Way, Ben Breech, Lori L. Pollock
VLSID
2000
IEEE
79views VLSI» more  VLSID 2000»
15 years 4 months ago
Inductive Noise Reduction at the Architectural Level
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv...
CC
2000
Springer
100views System Software» more  CC 2000»
15 years 4 months ago
A Static Study of Java Exceptions Using JESP
JESP is a tool for statically examining the usage of user thrown exceptions in Java source code. Reported here are the first findings over a dataset of 31 publicly available Java...
Barbara G. Ryder, Donald Smith, Ulrich Kremer, Mic...
ISLPED
1999
ACM
143views Hardware» more  ISLPED 1999»
15 years 4 months ago
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
Kanad Ghose, Milind B. Kamble
ISLPED
1999
ACM
84views Hardware» more  ISLPED 1999»
15 years 4 months ago
An architectural solution for the inductive noise problem due to clock-gating
As we approach Gigascale Integration, chip power consumption is becoming a critical system parameter. Clock-gating idle units provides needed reductions in power consumption. Howe...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv...