531 search results - page 23 / 107 » The Spec |
107
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IPPS
1999
IEEE
15 years 4 months ago
1999
IEEE
If parallelism can be successfully exploited in a program, significant reductions in execution time can be achieved. However, if sections of the code are dominated by parallel ove...
106
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HPCN
1998
Springer
15 years 4 months ago
1998
Springer
We propose a tunable scheduling strategy that lies between FIFO and shortest- rst, based on the value of a coe cient Alpha. If Alpha is set to zero then this strategy is just FIFO....
HPCA
1997
IEEE
15 years 4 months ago
1997
IEEE
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
MICRO
1997
IEEE
15 years 4 months ago
1997
IEEE
We propose a method for compressing programs in embedded processors where instruction memory size dominates cost. A post-compilation analyzer examines a program and replaces commo...
MICRO
1996
IEEE
15 years 4 months ago
1996
IEEE
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...