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HPCA
2002
IEEE
16 years 5 days ago
Quantifying Load Stream Behavior
The increasing performance gap between processors and memory will force future architectures to devote significant resources towards removing and hiding memory latency. The two ma...
Suleyman Sair, Timothy Sherwood, Brad Calder
HPCA
2001
IEEE
16 years 5 days ago
Dynamic Branch Prediction with Perceptrons
This paper presents a new method for branch prediction. The key idea is to use one of the simplest possible neural networks, the perceptron as an alternative to the commonly used ...
Daniel A. Jiménez, Calvin Lin
HPCA
2001
IEEE
16 years 5 days ago
Reducing DRAM Latencies with an Integrated Memory Hierarchy Design
In this papel; we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory syst...
Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
POPL
2007
ACM
16 years 3 days ago
Locality approximation using time
Reuse distance (i.e. LRU stack distance) precisely characterizes program locality and has been a basic tool for memory system research since the 1970s. However, the high cost of m...
Xipeng Shen, Jonathan Shaw, Brian Meeker, Chen Din...
ICCD
2006
IEEE
115views Hardware» more  ICCD 2006»
15 years 8 months ago
Microarchitecture and Performance Analysis of Godson-2 SMT Processor
—This paper introduces the microarchitecture and logical implementation of SMT (Simultaneous Multithreading) improvement of Godson-2 processor which is a 64-bit, four-issue, out-...
Zusong Li, Xianchao Xu, Weiwu Hu, Zhimin Tang