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ISPASS
2006
IEEE
15 years 5 months ago
Accelerating architectural exploration using canonical instruction segments
Detailed microarchitectural simulators are not well suited for exploring large design spaces due to their excessive simulation times. We introduce AXCIS, a framework for fast and ...
Rose F. Liu, Krste Asanovic
MICRO
2006
IEEE
111views Hardware» more  MICRO 2006»
15 years 5 months ago
Memory Prefetching Using Adaptive Stream Detection
We present Adaptive Stream Detection, a simple technique for modulating the aggressiveness of a stream prefetcher to match a workload’s observed spatial locality. We use this co...
Ibrahim Hur, Calvin Lin
MICRO
2006
IEEE
114views Hardware» more  MICRO 2006»
15 years 5 months ago
Authentication Control Point and Its Implications For Secure Processor Design
Secure processor architecture enables tamper-proof protection on software that addresses many difficult security problems such as reverse-engineering prevention, trusted computing...
Weidong Shi, Hsien-Hsin S. Lee
MICRO
2006
IEEE
132views Hardware» more  MICRO 2006»
15 years 5 months ago
Data-Dependency Graph Transformations for Superblock Scheduling
The superblock is a scheduling region which exposes instruction level parallelism beyond the basic block through speculative execution of instructions. In general, scheduling supe...
Mark Heffernan, Kent D. Wilken, Ghassan Shobaki
SCAM
2006
IEEE
15 years 5 months ago
Constructing Accurate Application Call Graphs For Java To Model Library Callbacks
Call graphs are widely used to represent calling relationships among methods. However, there is not much interest in calling relationships among library methods in many software e...
Weilei Zhang, Barbara G. Ryder