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IEEEPACT
2005
IEEE
15 years 5 months ago
Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors
Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes...
Yonghong Song, Spiros Kalogeropulos, Partha Tiruma...
IPPS
2005
IEEE
15 years 5 months ago
Using Performance Counters for Runtime Temperature Sensing in High-Performance Processors
As energy consumption in high-performance systems has increased, thermal management has become a big challenge. Providing a cost-effective and detailed temperature sensing mechani...
Kyeong-Jae Lee, Kevin Skadron
ISPASS
2005
IEEE
15 years 5 months ago
Balancing Performance and Reliability in the Memory Hierarchy
Cosmic-ray induced soft errors in cache memories are becoming a major threat to the reliability of microprocessor-based systems. In this paper, we present a new method to accurate...
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Ta...
ISPASS
2005
IEEE
15 years 5 months ago
Fast, Accurate Microarchitecture Simulation Using Statistical Phase Detection
Simulation-based microarchitecture research is often hindered by the slow speed of simulators. In this work, we propose a novel statistical technique to identify highly representa...
Ram Srinivasan, Jeanine Cook, Shaun Cooper
PRDC
2005
IEEE
15 years 5 months ago
Partitioned Cache Shadowing for Deep Sub-Micron (DSM) Regime
An important issue in modern cache designs is bridging the gap between wire and device delays. This warrants the use of more regular and modular structures to mask wire latencies....
Heng Xu, Arun K. Somani