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ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
15 years 4 months ago
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays
Microprocessor clock frequency has improved by nearly 40% annually over the past decade. This improvement has been provided, in equal measure, by smaller technologies and deeper p...
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler,...
ISCA
2002
IEEE
123views Hardware» more  ISCA 2002»
15 years 4 months ago
Going the Distance for TLB Prefetching: An Application-Driven Study
The importance of the Translation Lookaside Buffer (TLB) on system performance is well known. There have been numerous prior efforts addressing TLB design issues for cutting down ...
Gokul B. Kandiraju, Anand Sivasubramaniam
ISPAN
2002
IEEE
15 years 4 months ago
On the Impact of Naming Methods for Heap-Oriented Pointers in C Programs
Many applications written in C allocate memory blocks for their major data structures from the heap space at runtime. The analysis of heap-oriented pointers in such programs is cr...
Tong Chen, Jin Lin, Wei-Chung Hsu, Pen-Chung Yew
MICRO
2002
IEEE
97views Hardware» more  MICRO 2002»
15 years 4 months ago
Instruction fetch deferral using static slack
In this paper we present an approach to boosting performance and tolerating latency by deferring non-critical instructions into a deferred queue for later processing. As such, ins...
Gregory A. Muthler, David Crowe, Sanjay J. Patel, ...
MICRO
2002
IEEE
108views Hardware» more  MICRO 2002»
15 years 4 months ago
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
We describe the design, analysis, and performance of an on–line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MC...
Greg Semeraro, David H. Albonesi, Steve Dropsho, G...