531 search results - page 54 / 107 » The Spec |
MICRO
2002
IEEE
15 years 4 months ago
2002
IEEE
During the concept phase and definition of next generation high-end processors, power and performance will need to be weighted appropriately to deliver competitive cost/performan...
103
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WCRE
2002
IEEE
15 years 4 months ago
2002
IEEE
Dynamic binary translators compile machine code from a source architecture to a target architecture at run time. Due to the hard time constraints of just-in-time compilation only ...
121
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WCRE
2002
IEEE
15 years 4 months ago
2002
IEEE
Scientific, symbolic, and multimedia applications present diverse computing workloads with different types of inherent parallelism. Tomorrow’s processors will employ varying com...
LCTRTS
2001
Springer
15 years 4 months ago
2001
Springer
Computers are increasingly being incorporated in devices with a limited amount of available memory. As a result research is increasingly focusing on the automated reduction of pro...
HPCA
2000
IEEE
15 years 4 months ago
2000
IEEE
Clustered microarchitectures are an effective approach to reducing the penalties caused by wire delays inside a chip. Current superscalar processors have in fact a two-cluster mic...