531 search results - page 58 / 107 » The Spec |
ISCA
1997
IEEE
15 years 4 months ago
1997
IEEE
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....
MICRO
1997
IEEE
15 years 4 months ago
1997
IEEE
The multicluster architecture that we introduce offers a decentralized, dynamically-scheduled architecture, in which the register files, dispatch queue, and functional units of t...
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HPCA
1996
IEEE
15 years 4 months ago
1996
IEEE
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at pro...
PLDI
1994
ACM
15 years 3 months ago
1994
ACM
In this paper, we describe the program structure tree (PST), a hierarchical representation of program structure based on single entry single exit (SESE) regions of the control flo...
SIGMETRICS
1994
ACM
15 years 3 months ago
1994
ACM
Shade is an instruction-set simulator and custom trace generator. Application programs are executed and traced under the control of a user-supplied trace analyzer. To reduce commu...