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DSN
2005
IEEE
15 years 1 months ago
SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors
Soft errors are a growing concern for processor reliability. Recent work has motivated architecture-level studies of soft errors since the architecture can mask many raw errors an...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...
DSN
2005
IEEE
15 years 1 months ago
Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors
The increasing transient fault rate will necessitate onchip fault tolerance techniques in future processors. The speed gap between the processor and the memory is also increasing,...
Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt
EUROPAR
2008
Springer
15 years 1 months ago
Efficiently Building the Gated Single Assignment Form in Codes with Pointers in Modern Optimizing Compilers
Abstract. Understanding program behavior is at the foundation of program optimization. Techniques for automatic recognition of program constructs characterize the behavior of code ...
Manuel Arenaz, Pedro Amoedo, Juan Touriño
ISLPED
2007
ACM
84views Hardware» more  ISLPED 2007»
15 years 1 months ago
Towards a software approach to mitigate voltage emergencies
Increases in peak current draw and reductions in the operating voltages of processors continue to amplify the importance of dealing with voltage fluctuations in processors. One a...
Meeta Sharma Gupta, Krishna K. Rangan, Michael D. ...
ISLPED
2007
ACM
75views Hardware» more  ISLPED 2007»
15 years 1 months ago
Minimizing power dissipation during write operation to register files
This paper presents a power reduction mechanism for the write operation in register files (RegFiles), which adds a conditional charge-sharing structure to the pair of complementar...
Kimish Patel, Wonbok Lee, Massoud Pedram