531 search results - page 78 / 107 » The Spec |
102
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CGO
2007
IEEE
15 years 6 months ago
2007
IEEE
This paper proposes the use of empirical modeling techniques for building microarchitecture sensitive models for compiler optimizations. The models we build relate program perform...
101
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CGO
2007
IEEE
15 years 6 months ago
2007
IEEE
Run-time compilation systems are challenged with the task of translating a program’s instruction stream while maintaining low overhead. While software managed code caches are ut...
DATE
2007
IEEE
15 years 6 months ago
2007
IEEE
Deep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware compo...
117
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DSN
2007
IEEE
15 years 6 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
IEEEPACT
2007
IEEE
15 years 6 months ago
2007
IEEE
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...