531 search results - page 93 / 107 » The Spec |
ISCA
2010
IEEE
15 years 4 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
107
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CF
2010
ACM
15 years 4 months ago
2010
ACM
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
112
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IEEEPACT
2002
IEEE
15 years 4 months ago
2002
IEEE
Simultaneous Multithreading (SMT) processors achieve high processor throughput at the expense of single-thread performance. This paper investigates resource allocation policies fo...
103
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ISCA
2002
IEEE
15 years 4 months ago
2002
IEEE
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
ISCA
2002
IEEE
15 years 4 months ago
2002
IEEE
Techniques for analyzing and improving memory referencing behavior continue to be important for achieving good overall program performance due to the ever-increasing performance g...