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TJS
2002
135views more  TJS 2002»
15 years 4 months ago
HPCVIEW: A Tool for Top-down Analysis of Node Performance
Although it is increasingly difficult for large scientific programs to attain a significant fraction of peak performance on systems based on microprocessors with substantial instr...
John M. Mellor-Crummey, Robert J. Fowler, Gabriel ...
TPDS
2010
144views more  TPDS 2010»
15 years 2 months ago
Performance Evaluation of Dynamic Speculative Multithreading with the Cascadia Architecture
—Thread-level parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting instruction-level parallelism (ILP) on high-performance superscala...
David A. Zier, Ben Lee
LCPC
2001
Springer
15 years 9 months ago
The Structure of a Compiler for Explicit and Implicit Parallelism
Abstract. We describe the structure of a compilation system that generates code for processor architectures supporting both explicit and implicit parallel threads. Such architectur...
Seon Wook Kim, Rudolf Eigenmann
ESCIENCE
2007
IEEE
15 years 11 months ago
Performance Evaluation of Scheduling Policies for Volunteer Computing
BOINC, a middleware system for volunteer computing, allows hosts to be attached to multiple projects. Each host periodically requests jobs from project servers and executes the jo...
Derrick Kondo, David P. Anderson, John McLeod
133
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CLUSTER
2005
IEEE
15 years 10 months ago
Implementation and Performance of Portals 3.3 on the Cray XT3
The Portals data movement interface was developed at Sandia National Laboratories in collaboration with the University of New Mexico over the last ten years. Portals is intended t...
Ron Brightwell, Trammell Hudson, Kevin T. Pedretti...