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135
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DATE
2003
IEEE
131views Hardware» more  DATE 2003»
15 years 11 months ago
High Speed and Highly Testable Parallel Two-Rail Code Checker
In this article we propose a high speed and highly testable parallel two-rail code checker, which features a compact structure and is Totally-Self-Checking or Strongly Code-Disjoi...
Martin Omaña, Daniele Rossi, Cecilia Metra
ASPDAC
2005
ACM
133views Hardware» more  ASPDAC 2005»
15 years 8 months ago
A novel O(n) parallel banker's algorithm for System-on-a-Chip
This paper proposes a novel O(n) Parallel Banker’s Algorithm (PBA) with a best-case run-time of O(1), reduced from an ¢¤£¦¥¨§© run-time complexity of the original Ban...
Jaehwan John Lee, Vincent John Mooney III
ICPR
2004
IEEE
16 years 7 months ago
From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers
Parallel processors such as SIMD computers have been successfully used in various areas of high performance image and data processing. Due to their characteristics of highly regula...
Jie Han, Pieter Jonker
AINA
2006
IEEE
16 years 6 days ago
On Optimization and Parallelization of Fuzzy Connected Segmentation for Medical Imaging
Fuzzy Connectedness is an important image segmentation routine for image processing of medical images. It is often used in preparation for surgery and sometimes during surgery. It...
Christopher Gammage, Vipin Chaudhary
171
Voted
ASPLOS
2006
ACM
16 years 3 days ago
Accelerator: using data parallelism to program GPUs for general-purpose uses
GPUs are difficult to program for general-purpose uses. Programmers can either learn graphics APIs and convert their applications to use graphics pipeline operations or they can ...
David Tarditi, Sidd Puri, Jose Oglesby