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HIPC
2004
Springer
15 years 7 months ago
Parallel Performance of Hierarchical Multipole Algorithms for Inductance Extraction
Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip ...
Hemant Mahawar, Vivek Sarin, Ananth Grama
SBACPAD
2008
IEEE
206views Hardware» more  SBACPAD 2008»
15 years 8 months ago
A High Performance Massively Parallel Approach for Real Time Deformable Body Physics Simulation
Single processor technology has been evolving across last decades, but due to physical limitations of chip manufacturing process, the industry is pursuing alternatives to sustain ...
Thiago S. M. C. de Farias, Mozart W. S. Almeida, J...
WSC
1997
15 years 3 months ago
A Framework for Performance Analysis of Parallel Discrete Event Simulators
A framework for performance analysis of parallel discrete event simulators is presented. The centerpiece of this framework is a platform-independent Workload Specification Langua...
Vijay Balakrishnan, Peter Frey, Nael B. Abu-Ghazal...
SC
1995
ACM
15 years 5 months ago
A Performance Evaluation of the Convex SPP-1000 Scalable Shared Memory Parallel Computer
The Convex SPP-1000 is the first commercial implementation of a new generation of scalable shared memory parallel computers with full cache coherence. It employs a hierarchical s...
Thomas L. Sterling, Daniel Savarese, Peter MacNeic...
IPPS
2009
IEEE
15 years 8 months ago
The impact of network noise at large-scale communication performance
The impact of operating system noise on the performance of large-scale applications is a growing concern and ameliorating the effects of OS noise is a subject of active research. ...
Torsten Hoefler, Timo Schneider, Andrew Lumsdaine