4213 search results - page 618 / 843 » The Tau Parallel Performance System |
186
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ISCA
2011
IEEE
2011
IEEE
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
14 years 10 months ago
To meet the demand for more powerful high-performance shared-memory servers, multiprocessor systems must incorporate efficient and scalable cache coherence protocols, such as thos...
155
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RTSS
1989
IEEE
15 years 10 months ago
1989
IEEE
A new fault tolerant architecture that provides tolerance to a broad scope of hardware, software, and communications faults is being developed. This architecture relies on widely ...
173
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ICS
2005
Tsinghua U.
15 years 11 months ago
2005
Tsinghua U.
Excessive power consumption is becoming a major barrier to extracting the maximum performance from high-performance parallel systems. Therefore, techniques oriented towards reduci...
167
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ICDCS
2010
IEEE
15 years 8 months ago
2010
IEEE
Abstract—We propose RoLo (Rotated Logging), a new logging architecture for RAID10 systems for enhanced energy efficiency, performance and reliability. By spreading destaging I/O...
188
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VTC
2006
IEEE
16 years 5 days ago
2006
IEEE
— Bit interleaved coded multiple beamforming (BICMB) was previously designed to achieve full spatial multiplexing of min(N, M) and full spatial diversity of NM for N transmit and...