Sciweavers

4213 search results - page 665 / 843
» The Tau Parallel Performance System
Sort
View
COMPCON
1994
IEEE
15 years 9 months ago
Desktop Batch Processing
: Today, online transaction processing applications can downsize from mainframes to microprocessors. Commodity database systems, operating systems, and hardware came of age in 1993...
Jim Gray, Chris Nyberg
MICRO
2010
IEEE
270views Hardware» more  MICRO 2010»
15 years 2 months ago
Many-Thread Aware Prefetching Mechanisms for GPGPU Applications
Abstract-- We consider the problem of how to improve memory latency tolerance in massively multithreaded GPGPUs when the thread-level parallelism of an application is not sufficien...
Jaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim...
CCGRID
2006
IEEE
15 years 11 months ago
Proposal of MPI Operation Level Checkpoint/Rollback and One Implementation
With the increasing number of processors in modern HPC(High Performance Computing) systems, there are two emergent problems to solve. One is scalability, the other is fault tolera...
Yuan Tang, Graham E. Fagg, Jack Dongarra
ICS
2005
Tsinghua U.
15 years 10 months ago
The implications of working set analysis on supercomputing memory hierarchy design
Supercomputer architects strive to maximize the performance of scientific applications. Unfortunately, the large, unwieldy nature of most scientific applications has lead to the...
Richard C. Murphy, Arun Rodrigues, Peter M. Kogge,...
SASP
2008
IEEE
162views Hardware» more  SASP 2008»
15 years 11 months ago
Accelerating Compute-Intensive Applications with GPUs and FPGAs
—Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are F...
Shuai Che, Jie Li, Jeremy W. Sheaffer, Kevin Skadr...