4213 search results - page 681 / 843 » The Tau Parallel Performance System |
109
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ROBOCUP
2001
Springer
15 years 9 months ago
2001
Springer
Abstract. This paper presents the hardware and software design principles of the medium size RoboCup Team CoPS which are developed by the image understanding group at the Institute...
127
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EH
1999
IEEE
15 years 9 months ago
1999
IEEE
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reco...
150
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ISCA
1990
IEEE
15 years 9 months ago
1990
IEEE
An adaptive cache coherence mechanism exploits semantic information about the expected or observed access behavior of particular data objects. We contend that, in distributed shar...
154
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DEXAW
2007
IEEE
15 years 8 months ago
2007
IEEE
We built a system for the automatic creation of a textbased topic hierarchy, meant to be used in a geographically defined community. This poses two main problems. First, the appea...
ASPDAC
2005
ACM
15 years 6 months ago
2005
ACM
– We propose a System-on-Chip (SoC) architecture for reconfigurable applications based on the AMBA HighSpeed Bus (AHB). The architecture features multiple low-area flyby DMA bloc...