Sciweavers

4213 search results - page 728 / 843
» The Tau Parallel Performance System
Sort
View
3DPVT
2006
IEEE
183views Visualization» more  3DPVT 2006»
15 years 10 months ago
High-Quality Real-Time Stereo Using Adaptive Cost Aggregation and Dynamic Programming
We present a stereo algorithm that achieves high quality results while maintaining real-time performance. The key idea is simple: we introduce an adaptive aggregation step in a dy...
Liang Wang, Miao Liao, Minglun Gong, Ruigang Yang,...
HICSS
2006
IEEE
164views Biometrics» more  HICSS 2006»
15 years 10 months ago
A Methodology for Generating Application-Specific Heterogeneous Processor Arrays
Hardware designers are increasingly turning to Single Chip Multi-Processors to achieve power and throughput goals. To further increase performance for a specific application the c...
Stephen D. Craven, Cameron Patterson, Peter M. Ath...
ICPADS
2006
IEEE
15 years 10 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
ASPDAC
2006
ACM
143views Hardware» more  ASPDAC 2006»
15 years 10 months ago
Constraint-driven bus matrix synthesis for MPSoC
– Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based com...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
CCGRID
2005
IEEE
15 years 10 months ago
A distributed resource and network partitioning architecture for service grids
Abstract In this paper, we propose the use of a distributed service management architecture for state-of-the-art service-enabled Grids. The architecture is capable of performing au...
Bruno Volckaert, Pieter Thysebaert, Marc De Leenhe...