Sciweavers

4213 search results - page 748 / 843
» The Tau Parallel Performance System
Sort
View
ICDCSW
2002
IEEE
15 years 9 months ago
Quantifying Effect of Network Latency and Clock Drift on Time-Driven Key Sequencing
Time-driven Key Sequencing (TKS) is a key management technique that synchronizes the session key used by a set of communicating principals based on time of day. This relatively lo...
Geoffrey G. Xie, Cynthia E. Irvine, Timothy E. Lev...
HIPEAC
2009
Springer
15 years 8 months ago
HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
Suriya Subramanian, Kathryn S. McKinley
ARCS
2006
Springer
15 years 8 months ago
Estimating Energy Consumption for an MPSoC Architectural Exploration
Early energy estimation is increasingly important in MultiProcessor System-On-Chip (MPSoC) design. Applying traditional approaches, which consist in delaying the estimation until t...
Rabie Ben Atitallah, Smaïl Niar, Alain Greine...
139
Voted
ATS
2001
IEEE
126views Hardware» more  ATS 2001»
15 years 7 months ago
Design of an Optimal Test Access Architecture Using a Genetic Algorithm
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...
Zahra Sadat Ebadi, André Ivanov
CASES
2000
ACM
15 years 7 months ago
Flexible instruction processors
This paper introduces the notion of a Flexible Instruction Processor (FIP) for systematic customisation of instruction processor design and implementation. The features of our app...
Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung