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109
Voted
SPAA
2009
ACM
16 years 26 days ago
Optimizing transactions for captured memory
In this paper, we identify transaction-local memory as a major source of overhead from compiler instrumentation in software transactional memory (STM). Transaction-local memory is...
Aleksandar Dragojevic, Yang Ni, Ali-Reza Adl-Tabat...
135
Voted
VEE
2009
ACM
146views Virtualization» more  VEE 2009»
15 years 10 months ago
Demystifying magic: high-level low-level programming
r of high-level languages lies in their abstraction over hardware and software complexity, leading to greater security, better reliability, and lower development costs. However, o...
Daniel Frampton, Stephen M. Blackburn, Perry Cheng...
140
Voted
DATE
2007
IEEE
95views Hardware» more  DATE 2007»
15 years 10 months ago
Memory bank aware dynamic loop scheduling
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son,...
136
Voted
CASES
2006
ACM
15 years 9 months ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh
150
Voted
VLBV
2005
Springer
15 years 9 months ago
Coding with Temporal Layers or Multiple Descriptions for Lossy Video Transmission
In this paper, we compare temporal layered coding (TLC), as well as single-state coding (SSC), to multi-state video coding (MSVC) in the context of lossy video communications. MSV...
Sila Ekmekci Flierl, Thomas Sikora, Pascal Frossar...