4305 search results - page 107 / 861 » The Test of Time |
187
click to vote
DFT
2003
IEEE
15 years 11 months ago
2003
IEEE
Safety-critical embedded systems often operate in harsh environmental conditions that necessitate fault-tolerant computing techniques. Many safety-critical systems also execute re...
142
click to vote
ITC
2003
IEEE
15 years 11 months ago
2003
IEEE
A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 µ m TSMC process (CM018) to test chip I/O speeds, specifically, the setup and hold...
163
click to vote
ET
2000
15 years 5 months ago
2000
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
147
click to vote
ETS
2009
IEEE
15 years 3 months ago
2009
IEEE
This paper reports two novel algorithms based on time-modulo reconstruction method intended for detection of the parametric faults in analogue-to-digital converters (ADC). In both ...
162
click to vote
VTS
2007
IEEE
16 years 9 days ago
2007
IEEE
In SoC designs, limited test access to internal cores, lowcost external tester’s lack of accuracy and slow frequencies make application of at-speed tests impractical. Therefore,...