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ISSRE
2003
IEEE
15 years 5 months ago
Reducing wasted development time via continuous testing
Testing is often performed frequently during development to ensure software reliability by catching regression errors quickly. However, stopping frequently to test also wastes tim...
David Saff, Michael D. Ernst
94
Voted
JDCTA
2010
172views more  JDCTA 2010»
14 years 6 months ago
Performance Test of An Embedded Real-Time Operating System Based on A New High-Security NetWork Computer
Performance indexes of the embedded real-time operating system are not isolated but interacting with each other. Two sets of elements aiming to describe the relationship between t...
Gengxin Sun, Fengjing Shao Name, Sheng Bin
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
15 years 6 months ago
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon W...
DATE
1999
IEEE
102views Hardware» more  DATE 1999»
15 years 4 months ago
Minimal Length Diagnostic Tests for Analog Circuits using Test History
In this paper we propose an efficient transient test generation method to comprehensively test analog circuits using minimum test time. A divide and conquer strategy is formulated...
Alfred V. Gomes, Abhijit Chatterjee
79
Voted
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
15 years 5 months ago
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and co...
Sandeep Kumar Goel, Erik Jan Marinissen