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AIS
2004
Springer
15 years 3 months ago
Timed I/O Test Sequences for Discrete Event Model Verification
Abstract. Model verification examines the correctness of a model implementation with respect to a model specification. While being described from model specification, implementatio...
Ki Jung Hong, Tag Gon Kim
DATE
2003
IEEE
114views Hardware» more  DATE 2003»
15 years 5 months ago
A New Approach to Test Generation and Test Compaction for Scan Circuits
We propose a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors...
Irith Pomeranz, Sudhakar M. Reddy
ICST
2009
IEEE
14 years 9 months ago
Timed Testing under Partial Observability
This paper studies the problem of model-based testing of real-time systems that are only partially observable. We model the System Under Test (SUT) using Timed Game Automata (TGA)...
Alexandre David, Kim Guldstrand Larsen, Shuhao Li,...
DATE
2008
IEEE
86views Hardware» more  DATE 2008»
15 years 6 months ago
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testi...
Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Ric...
APSEC
2004
IEEE
15 years 3 months ago
Testing Java Interrupts and Timed Waits
Testing concurrent software is difficult due to problems with inherent non-determinism. In previous work, we have presented a method and tool support for the testing of concurrent...
Luke Wildman, Brad Long, Paul A. Strooper