Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Reduction of both the test suite size and the download time of test vectors is important in today's System-On-a-Chip designs. In this paper, a method for compressing the scan...
Michael J. Knieser, Francis G. Wolff, Christos A. ...
VLSI timing analysis and power estimation target the same circuit switching activity. Power estimation techniques are categorized as (1) static, (2) statistical, and (3) simulatio...
In this user study, we address several open issues in the design of waiting cues for system response time (SRT) in interactive telephony speech applications. User observations and...
We present a case study in which a novel testing tool, Quviq QuickCheck, is used to test an industrial implementation of the Megaco protocol. We considered positive and negative t...
Thomas Arts, John Hughes, Joakim Johansson, Ulf Wi...