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DATE
2008
IEEE
95views Hardware» more  DATE 2008»
15 years 6 months ago
Improvements in Polynomial-Time Feasibility Testing for EDF
This paper presents two fully polynomial-time sufficient feasibility tests for EDF when considering periodic tasks with arbitrary deadlines and preemptive scheduling on uniproces...
Alejandro Masrur, Sebastian Drossler, Georg Farber
ITC
1999
IEEE
67views Hardware» more  ITC 1999»
15 years 4 months ago
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
SEMATECH has sponsored a "Test Method Evaluation" study to understand the trade-offs among the most common test methodologies used in the industry[1,2]. This paper prese...
Phil Nigh, David P. Vallett, Atul Patel, Jason Wri...
ICSE
2007
IEEE-ACM
15 years 12 months ago
Using GUI Run-Time State as Feedback to Generate Test Cases
This paper presents a new automated model-driven technique to generate test cases by using feedback from the execution of a "seed test suite" on an application under tes...
Xun Yuan, Atif M. Memon
DFT
2003
IEEE
113views VLSI» more  DFT 2003»
15 years 5 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
ITC
2000
IEEE
80views Hardware» more  ITC 2000»
15 years 4 months ago
A stand-alone integrated test core for time and frequency domain measurements
An area efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstructi...
Mohamed Hafed, Nazmy Abaskharoun, Gordon W. Robert...