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ICCAD
2004
IEEE
101views Hardware» more  ICCAD 2004»
15 years 10 months ago
Frugal linear network-based test decompression for drastic test cost reductions
— In this paper we investigate an effective approach to construct a linear decompression network in the multiple scan chain architecture. A minimal pin architecture, complemented...
Wenjing Rao, Alex Orailoglu, G. Su
VLSID
2002
IEEE
78views VLSI» more  VLSID 2002»
16 years 2 months ago
Optimization of Test Accesses with a Combined BIST and External Test Scheme
External pins for test are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architectu...
Makoto Sugihara, Hiroto Yasuura
DATE
2006
IEEE
80views Hardware» more  DATE 2006»
15 years 8 months ago
Software-based self-test of processors under power constraints
Software-based self-test (SBST) of processors offers many benefits, such as dispense with expensive test equipments, test execution during maintenance and in the field or initiali...
Jun Zhou, Hans-Joachim Wunderlich
GI
2007
Springer
15 years 8 months ago
Industrial Requirements to Benefit from Test Automation Tools for GUI Testing
: In addition to the growing complexity of software systems, test effort takes increasing amounts of time and correspondingly more money. Testing costs may be reduced without compr...
Christof J. Budnik, Rajesh Subramanyan, Marlon Vie...
IESS
2007
Springer
110views Hardware» more  IESS 2007»
15 years 8 months ago
Run-Time efficient Feasibility Analysis of Uni-Processor Systems with Static Priorities
: The performance of feasibility tests is crucial in many applications. When using feasibility tests online only a limited amount of analysis time is available. Run-time efficiency...
Karsten Albers, Frank Bodmann, Frank Slomka