Sciweavers

4305 search results - page 31 / 861
» The Test of Time
Sort
View
ISQED
2003
IEEE
85views Hardware» more  ISQED 2003»
15 years 7 months ago
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanja...
120
Voted
EURODAC
1995
IEEE
198views VHDL» more  EURODAC 1995»
15 years 5 months ago
On generating compact test sequences for synchronous sequential circuits
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
Irith Pomeranz, Sudhakar M. Reddy
DFT
2003
IEEE
64views VLSI» more  DFT 2003»
15 years 7 months ago
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, ...
145
Voted
ECRTS
2006
IEEE
15 years 8 months ago
The Feasibility Analysis of Multiprocessor Real-Time Systems
The multiprocessor scheduling of collections of real-time jobs is considered. Sufficient tests are derived for determining whether a given collection of jobs can be scheduled to m...
Sanjoy K. Baruah, Nathan Fisher
DSD
2005
IEEE
106views Hardware» more  DSD 2005»
15 years 7 months ago
Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
1 This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detecte...
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles