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VTS
2003
IEEE
122views Hardware» more  VTS 2003»
15 years 11 months ago
A Reconfigurable Shared Scan-in Architecture
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
Samitha Samaranayake, Emil Gizdarski, Nodari Sitch...
AICCSA
2008
IEEE
290views Hardware» more  AICCSA 2008»
16 years 5 days ago
Test of preemptive real-time systems
Time Petri nets with stopwatches not only model system/environment interactions and time constraints. They further enable modeling of suspend/resume operations in real-time system...
Noureddine Adjir, Pierre de Saqui-Sannes, Kamel Mu...
ETS
2006
IEEE
113views Hardware» more  ETS 2006»
15 years 11 months ago
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. strate that these interconnects abstract the interconne...
Alexandre M. Amory, Kees Goossens, Erik Jan Marini...
ATS
2001
IEEE
126views Hardware» more  ATS 2001»
15 years 9 months ago
Design of an Optimal Test Access Architecture Using a Genetic Algorithm
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...
Zahra Sadat Ebadi, André Ivanov
ATS
2009
IEEE
132views Hardware» more  ATS 2009»
16 years 15 days ago
On Improving Diagnostic Test Generation for Scan Chain Failures
In this paper, we present test generation procedures to improve scan chain failure diagnosis. The proposed test generation procedures improve diagnostic resolution by using multi-...
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. ...