4305 search results - page 44 / 861 » The Test of Time |
124
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DATE
2003
IEEE
15 years 11 months ago
2003
IEEE
We propose a technique for compressing test vectors. The technique reduces test application time and tester memory requirements by utilizing part of the predecessor response in co...
137
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TCAD
2010
15 years 12 days ago
2010
Abstract--Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for...
164
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DDECS
2009
IEEE
15 years 9 months ago
2009
IEEE
Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated wi...
147
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VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
153
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DATE
2006
IEEE
15 years 11 months ago
2006
IEEE
Transparent-scan was proposed as an approach to test generation and test compaction for scan circuits. Its effectiveness was demonstrated earlier in reducing the test application ...