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DATE
2006
IEEE
98views Hardware» more  DATE 2006»
15 years 11 months ago
Power-constrained test scheduling for multi-clock domain SoCs
This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a t...
Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara
ETS
2010
IEEE
174views Hardware» more  ETS 2010»
15 years 6 months ago
Test-architecture optimization for TSV-based 3D stacked ICs
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D s...
Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakr...
AAAI
2007
15 years 8 months ago
The Impact of Time on the Accuracy of Sentiment Classifiers Created from a Web Log Corpus
We investigate the impact of time on the predictability of sentiment classification research for models created from web logs. We show that sentiment classifiers are time dependen...
Kathleen T. Durant, Michael D. Smith
CSSC
2010
123views more  CSSC 2010»
15 years 5 months ago
Testing Fractional Order of Long Memory Processes: A Monte Carlo Study
Testing the fractionally integrated order of seasonal and non-seasonal unit roots is quite important for the economic and financial time series modelling. In this paper, Robinson ...
Laurent Ferrara, Dominique Guegan, Zhiping Lu
TVLSI
2010
15 years 12 days ago
Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods
Abstract--Higher circuit densities in system-on-chip (SOC) designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requiremen...
Kanad Basu, Prabhat Mishra