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SERA
2005
Springer
15 years 11 months ago
A Design and Test Technique for Embedded Software
In recent years, embedded systems have become so complex and the development time to market is required to be shorter than before. As embedded systems include more functions for n...
Byeongdo Kang, Young-Jik Kwon, Roger Y. Lee
ITC
1998
IEEE
61views Hardware» more  ITC 1998»
15 years 10 months ago
Test session oriented built-in self-testable data path synthesis
Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of large design spa...
Han Bin Kim, Takeshi Takahashi, Dong Sam Ha
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
16 years 2 months ago
Extending the Applicability of Parallel-Serial Scan Designs
Although scan-based designs are widely used in order to reduce the complexity of test generation, test application time and test data volume are substantially increased. We propos...
Baris Arslan, Ozgur Sinanoglu, Alex Orailoglu
KBSE
2007
IEEE
16 years 4 hour ago
Test suite reduction and prioritization with call trees
This paper presents a tool that (i) constructs tree-based models of a program’s behavior during testing and (ii) employs these trees while reordering and reducing a test suite. ...
Adam M. Smith, Joshua Geiger, Gregory M. Kapfhamme...
ICCD
1999
IEEE
112views Hardware» more  ICCD 1999»
15 years 10 months ago
On Detecting Bridges Causing Timing Failures
High resistance bridges (resistive bridges) are becoming more common. Such bridges cause speed failures. Published experimental results show that current tests are not good at det...
Sreenivas Mandava, Sreejit Chakravarty, Sandip Kun...